Electrostatic chuck assembly with capacitive sense feature, and related operating method

ABSTRACT

A semiconductor workpiece processing system for treating a workpiece, such as a semiconductor wafer, is provided. A related operating control method is also provided. The system includes an electrostatic chuck configured to receive a workpiece, and a clamping voltage power supply coupled to the electrostatic chuck. The electrostatic chuck has a clamping electrode assembly, and the clamping voltage power supply is coupled to the clamping electrode assembly. The clamping voltage power supply includes a direct current (DC) voltage generator configured to generate a DC clamping voltage for the clamping electrode assembly, an alternating current (AC) voltage generator configured to generate an AC excitation signal for the clamping electrode assembly, and a processing architecture coupled to the clamping electrode assembly. The processing architecture is configured to analyze attributes of a workpiece presence signal obtained in response to the AC excitation signal, and, based on the attributes, verify proper/improper positioning of the workpiece relative to the electrostatic chuck.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of, and claims the benefit of thefiling date of, co-pending, nonprovisional U.S. patent application Ser.No. 12/052,395, filed on Mar. 20, 2008.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally toworkpiece processing. More particularly, embodiments of the subjectmatter relate to detecting processing status conditions of a workpiece,such as a semiconductor wafer, during processing and handling by asemiconductor workpiece processing system, such as a chemical vapordeposition system.

BACKGROUND

Electrostatic chucks are employed to support wafers in a variety ofsemiconductor workpiece processing systems. In a deposition system, forexample, an electrostatic chuck may be used to clamp a wafer in placewhile a thin film is deposited on the wafer. In an etch system, asanother example, an electrostatic chuck may be used to clamp a wafer inplace while material is being chemically etched from the wafer. Thesesystems typically comprise a reaction chamber, a vacuum pumping systemfor removing gases from the chamber, a reactant delivery system forconveying chemical reactants to the chamber, and a workpiece supportsystem for holding the workpiece in place during processing.

A typical workpiece support system employs a platen that supports theworkpiece during processing. Some systems also utilize electrostaticchucks, which use electrostatic force to hold the workpiece in place. Anelectrostatic chuck has electrodes that are energized with a clampingvoltage, which electrostatically clamps the wafer to the surface of theelectrostatic chuck. The electrodes in the electrostatic chuck arecoupled to an electrostatic power supply and a controller. Theelectrostatic power supply receives the control signal from thecontroller and generates a clamping voltage adapted to clamp thesubstrate with a clamping force.

Before the process begins, a wafer is transferred into the reactionchamber and is typically placed on lift pins that support the waferprior to loading onto the electrostatic chuck. The lift pins are thenlowered (and/or the electrostatic chuck is raised) such that the waferrests on the upper surface of the electrostatic chuck rather than on thelift pins. At this time, clamping voltage is applied to theelectrostatic chuck to clamp the wafer in preparation of the process.After completion of the process, the clamping voltage is removed torelease the wafer from the electrostatic chuck, and the lift pins areengaged to lift the wafer above the surface of the electrostatic chuck.Thereafter, the treated wafer can be removed from the lift pins using atransport mechanism.

Proper positioning of the wafer relative to the electrostatic chuck isimportant at various times before, during, and after typicalsemiconductor workpiece processes. For example, it is important toensure that the wafer is properly loaded onto the electrostatic chuckbefore applying the clamping voltage. As another example, it may bedesirable to determine whether the wafer is clamped or unclamped atcertain times. As yet another example, it can be important to ensurethat the wafer is properly positioned on the lift pins before proceedingfurther in the processing cycle.

BRIEF SUMMARY

An electrostatic chuck assembly suitable for use in a semiconductorworkpiece processing system and related operating methods are provided.The electrostatic chuck assembly includes a capacitive sensor subsystemthat is incorporated into the clamping voltage power supply of theelectrostatic chuck. The capacitive sensor subsystem applies anexcitation signal to the clamping electrodes of the electrostatic chuck,and determines wafer status conditions in response to the excitationsignal. In particular, changes in capacitance between the wafer and theelectrostatic chuck (which correspond to changes in the position of thewafer relative to the upper surface of the electrostatic chuck) resultin detectable attributes in a workpiece presence signal that is derivedfrom the excitation signal. The capacitive sensor subsystem detects andanalyzes these attributes before, during, and/or after the process toverify proper positioning of the wafer relative to the electrostaticchuck.

The above and other aspects may be found in an embodiment of anelectrostatic chuck assembly having: a platen configured to receive aworkpiece, an electrostatic chuck, an electrode assembly for the chuck,the electrode assembly being configured to receive a direct current (DC)clamping voltage to electrostatically adhere the workpiece to the chuck;and a capacitive sensor subsystem coupled to the electrode assembly. Thecapacitive sensor subsystem is configured to generate an alternatingcurrent (AC) excitation signal for the electrode assembly, and analyzeelectrical characteristics of the excitation signal that are influencedby changes in capacitance between the workpiece and the chuck.

The above and other aspects may be carried out by an embodiment of amethod of controlling a semiconductor workpiece processing system, thesystem having an electrostatic chuck that holds the workpiece duringprocessing. The method involves: applying an AC excitation signal toelectrodes of the electrostatic chuck; obtaining a workpiece presencesignal in response to the AC excitation signal, the workpiece presencesignal being influenced by capacitance between the electrostatic chuckand the workpiece; identifying an attribute of the workpiece presencesignal; and controlling operation of the system in a manner dictated bythe attribute.

The above and other aspects may be carried out by an embodiment of asystem having: an electrostatic chuck configured to receive a workpiece,the electrostatic chuck comprising a clamping electrode assembly; and aclamping voltage power supply coupled to the clamping electrodeassembly. The clamping voltage power supply includes: a DC voltagegenerator configured to generate a DC clamping voltage for the clampingelectrode assembly; an AC voltage generator configured to generate an ACexcitation signal for the clamping electrode assembly; and a processingarchitecture coupled to the clamping electrode assembly. The processingarchitecture is configured to analyze attributes of a workpiece presencesignal obtained in response to the AC excitation signal, and, based onthe attributes, verify proper/improper positioning of the workpiecerelative to the electrostatic chuck.

This summary is provided to introduce a selection of concepts in asimplified form that are further described below in the detaileddescription. This summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used as an aid in determining the scope of the claimed subjectmatter.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the subject matter may be derived byreferring to the detailed description and claims when considered inconjunction with the following figures, wherein like reference numbersrefer to similar elements throughout the figures.

FIG. 1 is a schematic representation of an embodiment of a CVD system;

FIG. 2 is a cross sectional view of an embodiment of an electrostaticchuck, showing engagement of lift pins;

FIG. 3 is a top view of the electrostatic chuck shown in FIG. 2;

FIG. 4 is a cross sectional view of the electrostatic chuck shown inFIG. 2, showing proper placement of a wafer on lift pins;

FIG. 5 is a cross sectional view of an embodiment of an electrostaticchuck, showing proper loading of a wafer;

FIG. 6 is a cross sectional view of an embodiment of an electrostaticchuck, showing improper loading of a wafer;

FIG. 7 is a schematic representation of an embodiment of anelectrostatic chuck assembly having a capacitive sensor subsystem;

FIG. 8 is a graph of an exemplary workpiece presence signal obtainedfrom a capacitance sensor subsystem of a semiconductor workpieceprocessing system during processing of a workpiece;

FIG. 9 is a flow chart that illustrates an embodiment of a method ofcontrolling a semiconductor workpiece processing system; and

FIG. 10 is a graph of an exemplary workpiece presence signal obtainedfrom a capacitance sensor subsystem of a semiconductor workpieceprocessing system during a self-clamp recovery procedure.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature andis not intended to limit the embodiments of the subject matter or theapplication and uses of such embodiments. As used herein, the word“exemplary” means “serving as an example, instance, or illustration.”Any implementation described herein as exemplary is not necessarily tobe construed as preferred or advantageous over other implementations.Furthermore, there is no intention to be bound by any expressed orimplied theory presented in the preceding technical field, background,brief summary or the following detailed description.

Techniques and technologies may be described herein in terms offunctional and/or logical block components, and with reference tosymbolic representations of operations, processing tasks, and functionsthat may be performed by various computing components or devices. Suchoperations, tasks, and functions are sometimes referred to as beingcomputer-executed, computerized, software-implemented, orcomputer-implemented. In practice, one or more processor devices cancarry out the described operations, tasks, and functions by manipulatingelectrical signals representing data bits at memory locations in thesystem memory, as well as other processing of signals. The memorylocations where data bits are maintained are physical locations thathave particular electrical, magnetic, optical, or organic propertiescorresponding to the data bits. It should be appreciated that thevarious block components shown in the figures may be realized by anynumber of hardware, software, and/or firmware components configured toperform the specified functions. For example, an embodiment of a systemor a component may employ various integrated circuit components, e.g.,memory elements, digital signal processing elements, logic elements,look-up tables, or the like, which may carry out a variety of functionsunder the control of one or more microprocessors or other controldevices.

The following description may refer to elements or nodes or featuresbeing “connected” or “coupled” together. As used herein, unlessexpressly stated otherwise, “connected” means that oneelement/node/feature is directly joined to (or directly communicateswith) another element/node/feature, and not necessarily mechanically.Likewise, unless expressly stated otherwise, “coupled” means that oneelement/node/feature is directly or indirectly joined to (or directly orindirectly communicates with) another element/node/feature, and notnecessarily mechanically.

As used herein, a “node” means any internal or external reference point,connection point, junction, signal line, conductive element, or thelike, at which a given signal, logic level, voltage, data pattern,current, or quantity is present. Furthermore, two or more nodes may berealized by one physical element (and two or more signals can bemultiplexed, modulated, or otherwise distinguished even though receivedor output at a common mode).

In addition, certain terminology may also be used in the followingdescription for the purpose of reference only, and thus are not intendedto be limiting. For example, terms such as “upper”, “lower”, “above”,and “below” refer to directions in the drawings to which reference ismade. Terms such as “front”, “back”, “rear”, “side”, “outboard,” and“inboard” describe the orientation and/or location of portions of thecomponent within a consistent but arbitrary frame of reference which ismade clear by reference to the text and the associated drawingsdescribing the component under discussion. Such terminology may includethe words specifically mentioned above, derivatives thereof, and wordsof similar import. Similarly, the terms “first”, “second” and other suchnumerical terms referring to structures do not imply a sequence or orderunless clearly indicated by the context.

The embodiments described below may be enabled in any manner ofsemiconductor workpiece processing system utilizing an electrostaticchuck. The system may be one of a chemical vapor deposition (CVD), highdensity plasma CVD (HDP-CVD), plasma-enhanced CVD (PECVD), physicalvapor deposition (PVD), atomic layer deposition (ALD), ion-enhanced ALD(iALD), resist strip, chemical etch, plasma etch, lithography or othersemiconductor processing system.

FIG. 1 is a schematic representation of an embodiment of an HDP-CVDsystem 100. For the sake of brevity, conventional techniques related tosemiconductor wafer processing, CVD processes, CVD systems andassociated system components, capacitive sensors, and other functionalaspects of the systems (and the individual operating components of thesystems) may not be described in detail herein. HDP-CVD system 100includes a process chamber 102 that encloses other components of HDP-CVDsystem 100 and serves to contain the plasma generated by an RF powersource coupled to an induction coil 104, which surrounds process chamber102 (on or embedded in the walls of process chamber 102). The walls ofprocess chamber 102 may be formed of aluminum, aluminum oxide, and/orother suitable material. Induction coil 104 is powered by a lowfrequency RF source 106. The power and frequency supplied by RF source106 is sufficient to generate high-density plasma from the process gas.

HDP-CVD system 100 includes a pedestal 108 that is configured to supporta workpiece 110, such as a semiconductor wafer undergoing a HDP-CVDprocess. In this embodiment, pedestal 108 includes an electrostaticchuck 112 that holds workpiece 110 in place during the depositionreaction. As described in more detail below, electrostatic chuck 112 maycooperate with a capacitive sensor subsystem for purposes of detectingcertain workpiece status conditions before, during, and/or after theHDP-CVD process. Moreover, electrostatic chuck 112 may be part of asuitably configured electrostatic chuck assembly as described herein.

A high frequency RF source 114 serves to electrically bias workpiece 110and draw charged precursor species onto workpiece 110 for the depositionor etch reactions. Electrical energy from RF source 114 is coupled toworkpiece 110 via an electrode or capacitive coupling, for example. Notethat the bias applied to workpiece 110 need not be an RF bias. Otherfrequencies and DC bias may be used as well.

The process gases are introduced via one or more chamber inlets 1 16.The gases may or may not be premixed. Additional inlets may be presentat any point in the process chamber. The process gases may include inertand reactive gases such as hydrogen, helium, argon, nitrogen, oxygen, orsilane. Preferably, the process gases are introduced through a gassupply inlet mechanism. The gas or gas mixture may be introduced from aprimary gas ring 117, which may or may not direct the gas toward thesurface of workpiece 110. In this embodiment, one or more ring inlets118 are connected to the primary gas ring 117 to supply gas or gasmixture into process chamber 102 via the chamber inlets 116. The sonicfront caused by the gas entering process chamber 102 will itself causethe gas to rapidly disperse in all directions, including towardworkpiece 110. The process gas exits process chamber 102 via one or moreoutlets 120. At least one vacuum pump (e.g., a turbomolecular pump) 122typically draws the gas out and maintains a suitably low pressure withinprocess chamber 102.

FIG. 2 is a simplified cross sectional view of an embodiment of anelectrostatic chuck 200, showing engagement of lift pins 202, and FIG. 3is a top view of electrostatic chuck 200. Electrostatic chuck 200 may beincorporated into a CVD system such as CVD system 100. In thisembodiment, electrostatic chuck 200 cooperates with three lift pins 202,arranged approximately 120 degrees apart from one another in atriangular layout (see FIG. 3). Lift pins 202 are suitably configuredand controlled to lift workpieces such as wafers above a platen 201 asneeded. In certain embodiments, lift pins 202 are formed from a ceramicmaterial, and their height positions relative to electrostatic chuck 200are controlled by the host semiconductor workpiece processing system.

Lift pins 202 are raised relative to electrostatic chuck 200 toaccommodate placement and removal of wafers onto a platen 201 ofelectrostatic chuck 200, where platen 201 is suitably configured toreceive the wafers. In this regard, FIG. 2 depicts lift pins 202 in alowered position where the upper tips of lift pins 202 reside below anupper surface 203 of electrostatic chuck 200. FIG. 4 is a simplifiedcross sectional view of electrostatic chuck 200, showing properplacement of a wafer 204 on lift pins 202. FIG. 4 depicts lift pins 202in a raised position where the upper tips of lift pins 202 reside aboveupper surface 203. While in this raised position, wafer 204 can beremoved from lift pins 202 by a suitably configured transport arm of thehost semiconductor workpiece processing system. As used herein, “proper”placement of a wafer on lift pins means that the wafer is resting on atleast the minimum number of lift pins required for support of the wafer.For the illustrated embodiment, proper placement of wafer 204 isachieved when wafer 204 is resting on all three lift pins 202, asdepicted in FIG. 4. Such proper placement results in a stable and flatpositioning of wafer 204 above electrostatic chuck 200. In contrast,“improper” placement means that wafer 204 is not in contact with one ormore lift pins 202. Such improper placement may cause wafer 204 to tiltor otherwise remain in an unstable position above electrostatic chuck200.

FIG. 5 is a cross sectional view of electrostatic chuck 200, showingproper loading of wafer 204 on upper surface 203. This particularembodiment of electrostatic chuck 200 includes a guard ring 206 and acavity 208 defined by guard ring 206 and upper surface 203. Guard ring206 may be a separate element that is coupled to the body ofelectrostatic chuck 200, or it may be integrally formed into the body ofelectrostatic chuck 200. In certain embodiments, electrostatic chuck 200and/or guard ring 206 are formed from a ceramic material. As shown inFIG. 3, guard ring 206 represents a circumferential boundary of cavity208, which is shaped and sized to accommodate wafer 204. As used herein,“proper” loading of a wafer means that the wafer is positionedcompletely within cavity 208, as depicted in FIG. 5. In practice, properloading in this manner is achieved before electrostatic chuck 200 isenergized to clamp wafer 204 against upper surface 203. In contrast,“improper” loading of a wafer means that the wafer is not positionedcompletely within cavity 208. In this regard, FIG. 6 is a crosssectional view of electrostatic chuck 200, showing one condition thatrepresents improper loading of wafer 204. Here, a portion of wafer 204rests on guard ring 206, which results in tilting of wafer 204 relativeto upper surface 203. As another example, wafer 204 is improperly loadedif it is skewed and completely resting on guard ring 206 (withouttouching upper surface 203). If electrostatic chuck 200 is energizedwith wafer 204 in an improperly loaded position, wafer 204 and/orelectrostatic chuck 200 might be damaged. At the very least, the qualityof the semiconductor workpiece process of an improperly loaded wafer 204will be significantly compromised.

An embodiment of a semiconductor workpiece processing system asdescribed herein employs an electrostatic chuck assembly, a clampingvoltage power supply, capacitive sensing technology, and a suitablyconfigured processing architecture to measure, detect, analyze, and/orverify certain conditions, status, or positioning of a wafer relative tothe electrostatic chuck. For example, the system (in particular, therelevant processing architecture) can be suitably configured to verifyproper/improper loading of a workpiece on the electrostatic chuck (asexplained above with reference to FIGS. 2-6). As another example, thesystem (in particular, the relevant processing architecture) can besuitably configured to verify proper/improper placement of a workpieceon the plurality of lift pins (as explained above with reference toFIGS. 2-6). Moreover, the system (in particular, the relevant processingarchitecture) can be suitably configured to verify proper/improperclamping of a workpiece to the electrostatic chuck (as described in moredetail below). In addition, the system can be suitably configured toperform a self-clamp recovery procedure that may be initiated when awafer remains electrostatically clamped to the electrostatic chuck afterremoval of the normal clamping voltage. This self-clamp recoveryprocedure is described in more detail below.

FIG. 7 is a schematic representation of an embodiment of anelectrostatic chuck assembly 300 having a capacitive sensor subsystem.Electrostatic chuck assembly 300 generally includes, without limitation,an electrostatic chuck 302 and a clamping voltage power supply 304coupled to electrostatic chuck 302. More specifically, electrostaticchuck 302 includes a clamping electrode assembly 306 for its platen,where clamping electrode assembly 306 is suitably configured to receivea direct current (DC) clamping voltage to electrostatically adhere aworkpiece 308 (such as a semiconductor wafer) to electrostatic chuck302. Moreover, the illustrated embodiment of clamping voltage powersupply 304 includes a capacitive sensor driver and processorarchitecture 310, and a DC voltage generator 312.

Clamping voltage power supply 304 may be realized as an integratedsubsystem of the host system, and FIG. 7 depicts a simplified embodimentfor ease of description. This embodiment of clamping voltage powersupply 304 has a positive voltage output node 314 and a negative voltageoutput node 316. Positive voltage output node 314 is coupled to oneelectrode 318 of clamping electrode assembly 306, and negative voltageoutput node 316 is coupled to another electrode 320 of clampingelectrode assembly 306. DC voltage generator 312 is suitably configuredto generate a DC clamping voltage for clamping electrode assembly 306,where the DC clamping voltage is applied via positive voltage outputnode 314 and negative voltage output node 316. An implementation of DCvoltage generator 312 may employ an adjustable positive DC voltagesource 322 and an adjustable negative DC voltage source 324, wherepositive DC voltage source 322 is controlled to generate an appropriatepositive DC potential at positive voltage output node 314 and negativeDC voltage source 324 is controlled to generate an appropriate negativeDC potential at negative voltage output node 316. Clamping electrodeassembly 306 responds to the relative voltage differential to establishthe necessary electrostatic clamping force. In certain embodiments, DCvoltage generator 312 may employ an adjustable DC offset voltage source326 as shown in FIG. 7. Offset voltage source 326 is coupled to positiveDC voltage source 322 and to negative DC voltage source 324, and offsetvoltage source 326 is configured to generate a DC offset potential forclamping electrode assembly 306.

Clamping voltage power supply 304 may also include one or more RFfilters 327 located between output nodes 314/316 and DC voltage sources322/324. RF filters 327 are suitably configured to filter high frequencyvoltage components that might otherwise enter clamping voltage powersupply 304. In one particular embodiment, for example, RF filters 327provide about 40 dBv of attenuation of 13.56 MHz and 400 kHz frequencycomponents.

Capacitive sensor driver and processor architecture 310 may beimplemented with any number of hardware, software, and/or firmwareelements that are appropriately configured and arranged to carry out thefunctions and operations described here. For example, this particularembodiment of architecture 310 includes an AC voltage generator 328 thatis configured to generate an AC excitation signal for clamping electrodeassembly 306. In some embodiments, the AC excitation signal has afrequency of about 1 kHz and a peak-to-peak voltage of about 20 volts.In other embodiments, the frequency range for deposition and etch can beabout 300 kHz to about 100 MHz. In one exemplary embodiment, a frequencyof about 400 kHz is used for ion source, and a frequency of about 13.56MHz is used for bias. Moreover, depending upon the actual processinvolved, the voltage can be within the range of about 100 Vrms to about1100 Vrms.

As described in more detail below, the capacitive sensor subsystemutilizes the AC excitation signal to detect changes in capacitancebetween workpiece 308 and electrostatic chuck 302. This embodiment of ACvoltage generator 328 cooperates with a positive AC voltage node 330 anda negative AC voltage node 332. In this embodiment, positive AC voltagenode 330 is coupled to electrode 318 of clamping electrode assembly 306,and negative AC voltage node 332 is coupled to electrode 320 of clampingelectrode assembly 306. Thus, AC voltage generator 328 applies the ACexcitation signal to clamping electrode assembly 306 via positive ACvoltage node 330 and negative AC voltage node 332. Under certainoperating conditions, AC voltage generator 328 is configured to impressthe AC excitation signal onto the DC clamping voltage generated by DCvoltage generator 312. In other words, clamping electrode assembly 306is concurrently subjected to the AC excitation signal and the DCclamping voltage. This enables the AC excitation signal to be appliedfor purposes of capacitive sensing before, during, and afterelectrostatic clamping of workpiece 308 to electrostatic chuck 302.

Capacitive sensor driver and processor architecture 310 can beconfigured and controlled to function as a capacitive sensor subsystemfor electrostatic chuck assembly 300, where the capacitive sensorsubsystem includes at least AC voltage generator 328 and a correspondingprocessing architecture that is able to analyze electricalcharacteristics of the AC excitation signal that are influenced bychanges in capacitance between workpiece 308 and the platen ofelectrostatic chuck 302. In practice, the processing architectureutilized to support the capacitive sensor subsystem may be implementedor performed with a general purpose processor, a content addressablememory, a digital signal processor, an application specific integratedcircuit, a field programmable gate array, any suitable programmablelogic device, discrete gate or transistor logic, discrete hardwarecomponents, or any combination designed to perform the functionsdescribed here. A processor may be realized as a microprocessor, acontroller, a microcontroller, or a state machine. Moreover, a processormay be implemented as a combination of computing devices, e.g., acombination of a digital signal processor and a microprocessor, aplurality of microprocessors, one or more microprocessors in conjunctionwith a digital signal processor core, or any other such configuration.

In response to the AC excitation signal, architecture 310 obtains andanalyzes certain attributes of a workpiece presence signal. As usedherein, an “attribute” of a workpiece presence signal is any measurable,detectable, calculable, or observable feature, value, trend, slope,characteristic, waveform, shape, or pattern of the workpiece presencesignal. Examples of such attributes include, without limitation: aparticular voltage level; a local or global minima or maxima; an abruptrise or fall in the signal; a change in the rising or falling slope inthe signal; or the like. An embodiment of the system described hereinmay utilize waveform analysis, signal processing, averaging, and/orcomparison techniques to analyze, detect, and identify certainattributes of interest.

Based on certain detected attributes of the workpiece presence signal,architecture 310 can verify proper or improper positioning of workpiece308 relative to electrostatic chuck 302 and/or lift pins 202. Suchverification is possible because electrical characteristics of theworkpiece presence signal are influenced by changes in capacitancebetween workpiece 308 and electrostatic chuck 302, and because suchcapacitance varies with the positioning of workpiece 308 relative toelectrostatic chuck 302. As described further below, architecture 310may be configured to detect workpiece status attributes of the workpiecepresence signal and, in response to detected workpiece statusattributes, control operation of the host semiconductor workpieceprocessing system. A workpiece status attribute may indicate, withoutlimitation: whether workpiece 308 is properly or improperly loaded onthe platen of electrostatic chuck 302; whether workpiece 308 is properlyclamped or unclamped to the platen; whether workpiece is restingproperly or improperly on the lift pins.

In operation, AC voltage generator 328 produces the AC excitationsignal, which is applied to clamping electrode assembly 306. Capacitivecurrents generated by the 1 kHz, 20 volt peak-to-peak excitation signalare interpreted as wafer capacitance. The capacitance current in thecircuit changes when the wafer is physically separated from the surfaceof the chuck. Architecture 310 monitors the workpiece presence signal,which has voltage characteristics that vary with the capacitance betweenworkpiece 308 and electrostatic chuck 302. In one practical embodiment,the capacitance is measured on a scale of zero to ten volts, based on1.8 V/nF. An embodiment of architecture 310 may process (e.g.,translate, encode, and/or amplify) the raw sense data to obtain aworkpiece presence signal having voltage characteristics that arecompatible with the hardware, software, and processing logic ofarchitecture 31 0. At specified times before, during, and afterprocessing of a workpiece, the workpiece presence signal is analyzed forcertain attributes, traits, and/or characteristics, such as voltagelevels. Then, architecture 310 can compare the detected attributes tocorresponding threshold values, calibrated values, or expected values todetermine or verify whether or not the positioning of workpiece 308relative to electrostatic chuck 302 (as indicated by the measuredcapacitance) is proper for that particular time. In practice,electrostatic chuck assembly 300 can perform workpiece positioningchecks at various times throughout a processing cycle.

FIG. 8 is a graph of an exemplary workpiece presence signal 400 obtainedfrom a capacitance sensor subsystem of a CVD system during processing ofa workpiece. It should be appreciated that workpiece presence signal 400represents only one possible sensor output, and that signals havingdifferent traits, characteristics, voltage levels, and timing can beproduced and monitored by a CVD system that implements an electrostaticchuck assembly as described herein. Moreover, the particularcharacteristics of a workpiece presence signal will be influenced by thespecific semiconductor workpiece processing system, the selected processrecipe, and other practical factors.

For ease of description, workpiece presence signal 400 depicted in FIG.8 represents a normal and error-free CVD process cycle. The left side ofFIG. 8 corresponds to the beginning of the CVD process cycle, when thewafer is present in the chamber but before the wafer is loaded onto theelectrostatic chuck. At this time, the wafer should be positioned on thelift pins as shown in FIG. 4. Plasma is present in the space between thewafer and the electrostatic chuck. The plasma serves as a very goodelectrical conductor and, therefore, the capacitance between the waferand the electrostatic chuck is very low under this condition.Accordingly, workpiece presence signal 400 is relatively high (e.g.,about 4.0 volts) before the wafer is loaded onto the chuck.

The first significant drop in workpiece presence signal 400 correspondsto the loading or placement of the wafer onto the upper surface of theelectrostatic chuck. This is due to the lowering of the lift pins. Atthis point, the wafer should be positioned as depicted in FIG.5—properly received within cavity 208 and not resting on guard ring 206.At or near time t₁, the capacitive sensor subsystem can verifyproper/improper placement of the wafer on the electrostatic chuck bycomparing the current voltage level of workpiece presence signal 400 toa given threshold voltage. In FIG. 8, the detected voltage correspondingto a properly loaded wafer is about 2.3 volts during a test period 402.For this example, a suitable threshold voltage for comparison at timet₁, might be about 2.0 volts. If the wafer is not properly loaded on theelectrostatic chuck, then the capacitance between the workpiece and theelectrostatic chuck will be higher and, as a result, workpiece presencesignal 400 will be less than 2.0 volts at time t₁. Accordingly, if thecapacitance sensor subsystem detects less than 2.0 volts at time t₁,then it will assume that the wafer is not properly loaded on theelectrostatic chuck.

At or near time t_(C), the DC clamping voltage is applied to theelectrostatic chuck to clamp the wafer. In practice, the CVD system mayperform a heating procedure between time t₁ and time t_(C) to preparethe wafer for the CVD process. The rise in workpiece presence signal 400at time t_(C) corresponds to the activation of the DC clamping voltage.This condition (which is sometimes referred to as “hard clamping”) isachieved when the wafer is electrostatically forced against theelectrostatic chuck. The DC clamping voltage causes the wafer to flattenagainst the electrostatic chuck. Consequently, the capacitance betweenthe wafer and the electrostatic chuck decreases and workpiece presencesignal 400 increases. In FIG. 8, the detected voltage corresponding to aproperly clamped wafer is about 3.0 volts during a test period 404. Itmay be desirable to check the sensed voltage at this time to confirmwhether or not the wafer is properly clamped. For this example, asuitable threshold voltage for comparison at time t₂ might be about 2.7volts. If the wafer is not properly clamped at this time, then thecapacitance between the workpiece and the electrostatic chuck will behigher and, as a result, workpiece presence signal 400 will be less than2.7 volts at time t₂. Accordingly, if the capacitance sensor subsystemdetects less than about 2.7 volts at time t₂, then it will assume thatthe wafer is not properly clamped to the electrostatic chuck.

At or near time t_(UC), the DC clamping voltage is removed from theelectrostatic chuck to unclamp the wafer. During the time between timet_(C) and time t_(UC), the CVD system performs the CVD process on thewafer. Also during this time, the wafer may be subjected to a coolingprocedure and/or a backside helium purge procedure following the CVDprocess. The drop in workpiece presence signal 400 at time t_(UC)corresponds to the removal of the DC clamping voltage and any DC offsetvoltage and, in response, removal of the electrostatic adhesion force.Thus, the wafer is freed from the electrostatic chuck. Since the waferneed not be completely flat in its natural state, removal of the DCclamping force can result in the wafer “springing” back into its naturalshape, which might cause the wafer to partially “float” above thesurface of the electrostatic chuck. Consequently, the capacitancebetween the wafer and the electrostatic chuck increases and workpiecepresence signal 400 decreases. In FIG. 8, the detected voltagecorresponding to a properly unclamped wafer is about 1.7 volts during atest period 406. At or near time t₃, the capacitance sensor subsystemcan check whether the wafer is in an unclamped state by comparing thevoltage level of workpiece presence signal 400 to a specified thresholdvoltage. For this example, a suitable threshold voltage for comparisonat time t₃ might be about 2.5 volts. If the wafer is not unclamped, thenthe capacitance between the workpiece and the electrostatic chuck willbe lower and, as a result, workpiece presence signal 400 will be greaterthan 2.5 volts at time t₃. Accordingly, if the capacitance sensorsubsystem detects more than 2.5 volts at time t₃, then it will assumethat the wafer is still at least partially clamped to the electrostaticchuck.

For this particular example, the detected unclamped voltage after theprocess (1.7 volts) is lower than the unclamped voltage before theprocess (2.3 volts). This is due to the fact that wafers are notperfectly flat and as the wafer is clamped it will flatten. A clampedwafer will experience thermal stresses during processing and after thewafer is unclamped it will return to its original state. During thistransition there is a period where the wafer oscillates giving the lowerdetected voltage (1.7 volts). The detected voltage will return to thehigher value (2.3 volts) once the oscillation stops.

At or near time t_(L), the lift pins are engaged to lift the wafer abovethe electrostatic chuck. The rise in workpiece presence signal 400 attime t_(L) corresponds to the lifting of the wafer above the uppersurface of the electrostatic chuck. Ideally, the wafer will be properlyresting on the lift pins at this time. For this particular embodiment,the plasma serves as a good conductor between the workpiece and theelectrostatic chuck. Consequently, the capacitance between the wafer andthe electrostatic chuck decreases and workpiece presence signal 400increases. In FIG. 8, the detected voltage corresponding to a properlylifted wafer is about 4.0 volts during a test period 408. At or neartime t₄, the capacitance sensor subsystem can verify whether the waferis properly or improperly resting on the lift pins by comparing thevoltage level of workpiece presence signal 400 to a specified thresholdvoltage. For this example, a suitable threshold voltage for comparisonat time t₄ might be about 3.8 volts. If the wafer is not properlyresting on the lift pins, then the capacitance between the workpiece andthe electrostatic chuck will be higher and, as a result, workpiecepresence signal 400 will be less than 3.8 volts at time t₄. Accordingly,if the capacitance sensor subsystem detects less than 3.8 volts at timet₄, then it will assume that the wafer is not resting properly on thelift pins.

In practice, a CVD system as described herein may need to be calibratedto ensure that the various threshold voltages accurately reflect theexpected trends in the workpiece presence signal. If the capacitivesensor subsystem is implemented in the clamping voltage power supply,then it may be desirable to calibrate the voltage thresholds wheneverthe clamping voltage power supply is replaced. Moreover, it may benecessary to calibrate the voltage thresholds for differentelectrostatic chuck configurations. Accordingly, the capacitive sensorsubsystem may have multiple calibration settings for multipleelectrostatic chuck types and/or multiple process sequences.

The capacitive sensing techniques described herein can be utilized tomonitor and/or control the operation of any semiconductor workpieceprocessing system that utilizes an electrostatic chuck. In this regard,FIG. 9 is a flow chart that illustrates an embodiment of a method 500 ofcontrolling a semiconductor workpiece processing system. The varioustasks performed in connection with method 500 may be performed bysoftware, hardware, firmware, or any combination thereof. Forillustrative purposes, the following description of method 500 may referto elements mentioned above in connection with FIGS. 1-7. In practice,portions of method 500 may be performed by different elements of thedescribed system, e.g., the electrostatic chuck, the clamping powersupply, a processing component, or the like. It should be appreciatedthat method 500 may include any number of additional or alternativetasks, the tasks shown in FIG. 9 need not be performed in theillustrated order, and method 500 may be incorporated into a morecomprehensive procedure or method having additional functionality notdescribed in detail herein.

For purposes of this example, semiconductor workpiece processing systemcontrol method 500 begins by applying an AC excitation signal (task 502)to the electrodes of the electrostatic chuck of the host system. Inaddition, method 500 obtains a suitably formatted workpiece presencesignal (task 504) in response to the AC excitation signal. As mentionedabove, the workpiece presence signal is influenced by the capacitancebetween the workpiece and the electrostatic chuck, and certainelectrical characteristics of the workpiece presence signal will varywith changes in the capacitance. This embodiment of method 500 thenbegins the processing operation (task 506) for a particular workpiece.Notably, the capacitive sensing technique described here is activebefore, during, and after the actual process that is performed by thesemiconductor workpiece processing system.

System control method 500 can analyze the workpiece presence signal atappropriate times during operation of the system. In certainembodiments, method 500 analyzes the workpiece presence signal toidentify (task 508) certain attributes of the workpiece presence signal,where such attributes are indicative of proper or improper positioningof the workpiece relative to the electrostatic chuck at differentmeasurement times during operation of the system. As explained abovewith reference to FIG. 8, method 500 may compare the measured voltage ofthe workpiece presence signal to one or more threshold voltages and/orcheck whether the measured voltage of the workpiece presence signal iswithin a proper range for the particular measurement time. In thisregard, query task 510 may represent a comparison of the sensed voltageto one or more calibrated threshold voltages associated with themeasurement time. In practice, different threshold voltages can be usedat different test times. As described above, the attribute identifiedduring task 508 may be indicative of: proper/improper placement of theworkpiece on the electrostatic chuck; a clamped/unclamped status of theworkpiece; proper/improper placement of the workpiece on a plurality oflift pins; or other conditions.

If query task 510 determines that the measured sense voltage is withinthe proper range for that measurement time, then system control method500 can proceed normally (task 512). Otherwise, method 500 may take anynecessary action (task 514), such as corrective action, termination ofthe operation step, generation of warnings or alarms, or the like. Forthis embodiment, method 500 controls the operation of the host system ina manner that is dictated by the detected attribute or attributes (task516). For example, if the attribute is indicative of proper initialplacement of the workpiece on the electrostatic chuck, then task 516 mayinitiate electrostatic clamping of the workpiece. If, however, theattribute is indicative of improper placement of the workpiece on theelectrostatic chuck, then task 516 may generate an appropriate warningindication, alarm, or message. Alternatively or additionally, task 516may cause the semiconductor workpiece processing system to initiatereloading of the workpiece on the electrostatic chuck in an attempt toobtain proper placement. Alternatively or additionally, task 516 mayterminate the operation step of the system if the detected attributeindicates improper placement of the workpiece on the electrostaticchuck. As another example, task 516 may generate indicia of the clampedor unclamped status of the workpiece. Referring to FIG. 8, this mightoccur at time t₂ (normally a clamped condition) or at time t₃ (normallyan unclamped condition). If the clamping status of the workpiece is notas expected, then task 516 may cause the system to terminate theoperation step, generate a warning, initiate a re-clamping procedure, orthe like. As yet another example, task 516 may generate an appropriatewarning message, signal, or alarm if the detected attribute isindicative of improper placement of the workpiece on the lift pins.Alternatively or additionally, task 516 may cause the semiconductorworkpiece processing system to initiate reloading of the workpiece onthe lift pins in an attempt to obtain proper placement. Alternatively oradditionally, task 516 may terminate the operation step of the system ifthe detected attribute indicates improper placement of the workpiece onthe lift pins. This type of corrective action may be desirable toprevent damage to the workpiece and/or to the system itself.

If the operation is complete (query task 518), then system controlmethod 500 ends or is repeated for the next workpiece. If the operationis not complete, then method 500 may return to task 508 to continuemonitoring for other detectable attributes and to continue operating thesemiconductor workpiece processing system in an appropriate manner asdescribed above.

A capacitive sensor subsystem as described herein can also be configuredand controlled to perform a self-clamp recovery procedure on a workpieceduring a semiconductor process operation. Self clamping is a problemcondition that can occur if, during processing, the wafer separates fromthe electrostatic chuck (this can be caused by the backside heliumpressure applied to the wafer, for example). Such separation of thewafer exposes the surface of the electrostatic chuck to the plasma,which can cause ionic charge to accumulate on the surface of the chuck.If the surface of the chuck is exposed to the plasma while clampingvoltage is applied, the surface of the chuck collects ions (charge).Consequently, even after the DC clamping voltage is removed from theelectrostatic chuck, the residual charge collected on the surface of thechuck attracts the wafer, resulting in partial electrostatic clamping tothe chuck. This condition can be problematic because most systemsordinarily expect the wafer to be free of the electrostatic chuck afterthe clamping voltage is removed, when in reality it remains clamped.

Referring again to FIG. 8, the check performed at time t₃ verifieswhether or not the workpiece is unclamped (as it should be under normaloperating conditions). If residual self-clamping has occurred during theprocess, then the sense voltage detected at time t₃ will be higher thanthe comparison threshold voltage. In other words, the capacitive sensorsubsystem will indicate that the workpiece is not in the desiredunclamped state. At this time, certain system embodiments can initiate aself-clamp recovery procedure in an attempt to release the workpiecefrom the electrostatic chuck before proceeding further.

For this particular embodiment, the self-clamp recovery proceduresearches for a “release” voltage that (when applied to the electrostaticchuck) releases the self-clamped wafer. In other words, the recoveryprocedure determines a compensating DC voltage that counteracts andnullifies the accumulated residual charge on the surface of theelectrostatic chuck. This is accomplished by applying different clampingvoltages to the electrostatic chuck while simultaneously monitoring theworkpiece presence signal (obtained by a capacitive sensor subsystem, asdescribed above). As different DC voltages are applied, certain voltagesor voltage ranges will release the workpiece from the electrostaticchuck, notwithstanding the accumulated residual charge. By monitoringand detecting certain attributes of the workpiece presence signal (inthe manner described above), the capacitive sensor subsystem can detectwhen the workpiece becomes unclamped and record or save thecorresponding DC voltage that results in unclamping. This allows thesemiconductor workpiece processing system to unclamp the workpiece byapplying the appropriate DC voltage to the electrostatic chuck. Afterthe workpiece is verified to be unclamped, the process operation mayproceed as usual or it may initiate corrective action to remove theresidual charge and then proceed as needed.

FIG. 10 graphically illustrates an exemplary self-clamp recoveryprocedure. FIG. 10 is a graph of an exemplary workpiece presence signal600 obtained from a capacitance sensor subsystem of a CVD system duringa self-clamp recovery procedure. FIG. 10 also includes a voltage scanplot 602 (which is V-shaped in this example) that represents the DCvoltage that is applied to the electrostatic chuck during the self-clamprecovery procedure. For this example, the vertical scale represents theDC voltage potential applied across two electrodes of the electrostaticchuck. For ease of description and illustration, no vertical scale isdepicted for workpiece presence signal 600.

The relatively flat region 604 of workpiece presence signal 600represents a clamped state, where residual self-clamping charge(combined with the applied DC voltage) clamps the workpiece to theelectrostatic chuck. In contrast, the lower extremes of workpiecepresence signal 600 indicate an unclamped state, where the applied DCvoltage counteracts the residual charge. For this example, thecapacitive sensor subsystem is suitably configured to detect at leastone local minimum in workpiece presence signal 600, where the localminimum is flanked by two local maxima. FIG. 10 depicts two of theselocal minima, which occur in two M-shaped regions 606/608. The localminimum point 610 is indicative of a first unclamped state, and thelocal minimum point 612 is indicative of a second unclamped state.

In operation, the DC voltage applied to the electrostatic chuck isvaried while workpiece presence signal 600 is monitored to detect theoccurrence of local minimum points 610/612. In practice, the same DCoffset voltage is used for workpiece processing and for the self-clamprecovery procedure. The example of FIG. 10 varies the DC voltage from amaximum value of about 4000 volts, to a minimum value of about zerovolts, and back to the maximum value. Other embodiments can scan the DCvoltage values in different ways. At or near time t₁, an applied DCvoltage of about 3000 volts results in the first unclamped statecorresponding to local minimum point 610. For comparison, under normalconditions where self-clamping has not occurred, an unclamped state isobtained when the DC voltage applied to the electrostatic chuck is at ornear zero volts. Likewise, at or near time t₂, an applied DC voltage ofabout 3000 volts results in the second unclamped state corresponding tolocal minimum point 612. This redundant check, while not required, isdesirable to ensure that the proper self-clamp recovery voltage isfound.

The capacitive sensor subsystem can then record the voltage or voltagesthat resulted in the unclamped condition (3000 volts in this example).This voltage is then applied to the electrostatic chuck to release theworkpiece. Application of the self-clamp recovery voltage should resultin an unclamped condition that can be verified in the manner describedabove in connection with FIG. 8.

The subject matter and embodiments described here may be implemented inany semiconductor workpiece processing reactor utilizing anelectrostatic chuck. Such a reactor may perform different deposition oretch/strip process and take many different forms. Generally, theapparatus will include one or more reaction chambers (sometimesincluding multiple stations) that house one or more wafers and aresuitable for wafer processing. The one or more chambers maintain thewafer in a defined position or positions (with or without motion withinthat position, e.g., rotation, vibration, or other agitation). While inprocess, each wafer is held in place by an electrostatic chuck and otherwafer holding apparatus. Examples of suitable reactors are the SPEED™HDP-CVD reactor, PDL™ silicon oxide reactor, and INOVA™ PVD reactor, allavailable from Novellus Systems, Inc. of San Jose, Calif.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiment or embodiments described herein are not intended tolimit the scope, applicability, or configuration of the claimed subjectmatter in any way. Rather, the foregoing detailed description willprovide those skilled in the art with a convenient road map forimplementing the described embodiment or embodiments. It should beunderstood that various changes can be made in the function andarrangement of elements without departing from the scope defined by theclaims, which includes known equivalents and foreseeable equivalents atthe time of filing this patent application.

1. An electrostatic chuck assembly comprising: a platen configured toreceive a workpiece; a clamping voltage power supply configured togenerate a direct current (DC) clamping voltage for the electrostaticchuck assembly; an electrode assembly for the platen, the electrodeassembly being configured to receive the DC clamping voltage toelectrostatically adhere the workpiece to the platen; and a capacitivesensor subsystem coupled to the electrode assembly, the capacitivesensor subsystem being configured to generate an alternating current(AC) excitation signal for the electrode assembly, and analyzeelectrical characteristics of the excitation signal that are influencedby changes in capacitance between the workpiece and the platen; whereinthe clamping voltage power supply comprises the capacitive sensorsubsystem; and the clamping voltage power supply further comprises anadjustable DC offset voltage source configured to generate a DC offsetpotential for the electrode assembly.
 2. The electrostatic chuckassembly of claim 1, the capacitive sensor subsystem comprising an ACvoltage generator configured to generate the AC excitation signal. 3.The electrostatic chuck assembly of claim 2, wherein the AC voltagegenerator is configured to impress the AC excitation signal onto the DCclamping voltage.
 4. The electrostatic chuck assembly of claim 1, thecapacitive sensor subsystem comprising a processing architectureconfigured to detect a workpiece status attribute of the excitationsignal.
 5. The electrostatic chuck assembly of claim 4, the processingarchitecture being further configured to control operation of a hostworkpiece processing system in response to the detected workpiece statusattribute.
 6. The electrostatic chuck assembly of claim 4, wherein theworkpiece status attribute indicates whether the workpiece is properlypositioned on the platen.
 7. The electrostatic chuck assembly of claim4, wherein the workpiece status attribute indicates whether theworkpiece is properly clamped to the platen.
 8. The electrostatic chuckassembly of claim 4, wherein: the electrostatic chuck assembly furthercomprises a plurality of lift pins configured to lift the workpieceabove the platen; and the workpiece status attribute indicates whetherthe workpiece is resting properly on the plurality of lift pins.
 9. Theelectrostatic chuck assembly of claim 1, wherein: the workpiececomprises a semiconductor wafer; and the electrostatic chuck assembly isincorporated into one of a deposition, etch, or strip system.
 10. Theelectrostatic chuck assembly of claim 9, wherein the deposition systemis a chemical vapor deposition system.
 11. The electrostatic chuckassembly of claim 10, wherein the deposition system is a high densityplasma chemical vapor deposition system.
 12. (canceled)
 13. A method ofcontrolling a semiconductor workpiece processing system that processes aworkpiece, the system having an electrostatic chuck that holds theworkpiece during processing, the method comprising: before performingworkpiece processing on the workpiece, applying an alternating current(AC) excitation signal to electrodes of the electrostatic chuck; beforeperforming workpiece processing on the workpiece, obtaining a workpiecepresence signal in response to the AC excitation signal, the workpiecepresence signal being influenced by capacitance between theelectrostatic chuck and the workpiece; before performing workpieceprocessing on the workpiece, identifying an attribute of the workpiecepresence signal; generating a warning indication before performingworkpiece processing on the workpiece, if the attribute is indicative ofimproper placement of the workpiece on the electrostatic chuck; andthereafter applying a constant DC clamping voltage to the electrostaticchuck while performing workpiece processing on the workpiece. 14.(canceled)
 15. (canceled)
 16. The method of claim 13, further comprisinginitiating reloading of the workpiece on the electrostatic chuck if theattribute is indicative of improper placement of the workpiece on theelectrostatic chuck.
 17. The method of claim 13, further comprisingterminating an operating step of the system if the attribute isindicative of improper placement of the workpiece on the electrostaticchuck.
 18. The method of claim 13, wherein the attribute is indicativeof a clamped/unclamped status of the workpiece on the electrostaticchuck.
 19. The method of claim 18, further comprising generating indiciaof the clamped/unclamped status.
 20. The method of claim 13, wherein:the electrostatic chuck cooperates with a plurality of lift pins; andthe attribute is indicative of proper/improper placement of theworkpiece on the plurality of lift pins.
 21. The method of claim 20,further comprising generating a warning indication if the attribute isindicative of improper placement of the workpiece on the plurality oflift pins.
 22. The method of claim 20, further comprising initiatingreloading of the workpiece on the plurality of lift pins if theattribute is indicative of improper placement of the workpiece on theplurality of lift pins.
 23. The method of claim 20, further comprisingterminating an operating step of the system if the attribute isindicative of improper placement of the workpiece on the plurality oflift pins.
 24. The method of claim 13, wherein: obtaining the workpiecepresence signal occurs at a measurement time; identifying an attributeof the workpiece presence signal comprises identifying a measuredvoltage of the workpiece presence signal at the measurement time; andthe method further comprises comparing the measured voltage to athreshold voltage associated with the measurement time.
 25. The methodof claim 13, wherein the semiconductor workpiece processing system is achemical vapor deposition system.
 26. The method of claim 25, whereinthe deposition system is a high density plasma chemical vapor depositionsystem.
 27. A semiconductor workpiece processing system comprising: anelectrostatic chuck configured to receive a workpiece, the electrostaticchuck comprising a clamping electrode assembly; and a clamping voltagepower supply coupled to the clamping electrode assembly, the clampingvoltage power supply comprising: a direct current (DC) voltage generatorconfigured to generate a DC clamping voltage for the clamping electrodeassembly; an adjustable DC offset voltage source configured to generatea DC offset potential for the clamping electrode assembly; analternating current (AC) voltage generator configured to generate an ACexcitation signal for the clamping electrode assembly; and a processingarchitecture coupled to the clamping electrode assembly, and configuredto analyze attributes of a workpiece presence signal obtained inresponse to the AC excitation signal, and, based on the attributes,verify proper/improper positioning of the workpiece relative to theelectrostatic chuck before and after performing workpiece processing onthe workpiece, wherein the clamping voltage power supply applies aconstant DC clamping voltage to the electrostatic chuck while thesemiconductor workpiece processing system performs workpiece processingon the workpiece.
 28. The system of claim 27, wherein the processingarchitecture is configured to verify proper/improper loading of theworkpiece on the electrostatic chuck before the semiconductor workpieceprocessing system performs workpiece processing on the workpiece. 29.The system of claim 27, wherein the processing architecture isconfigured to verify proper/improper clamping of the workpiece to theelectrostatic chuck before the semiconductor workpiece processing systemperforms workpiece processing on the workpiece.
 30. The system of claim27, further comprising a plurality of lift pins that cooperate with theelectrostatic chuck, wherein the processing architecture is configuredto verify proper/improper placement of the workpiece on the plurality oflift pins before the semiconductor workpiece processing system performsworkpiece processing on the workpiece.
 31. The system of claim 27,wherein electrical characteristics of the workpiece presence signal areinfluenced by changes in capacitance between the workpiece and theelectrostatic chuck.
 32. The system of claim 27, wherein thesemiconductor workpiece processing system is a chemical vapor depositionsystem.
 33. The method of claim 27, wherein the deposition system is ahigh density plasma chemical vapor deposition system.